The subject matter relates to a semiconductor memory device, and more particularly to a transistor layout in a sub hole region of a semiconductor memory device.
A semiconductor memory device such as a dynamic random access memory (DRAM) includes an interface region, a core region, and a hierarchical data bus structure for transferring data between the interface region and the core region. Segment input/output lines and local input/output lines are disposed in the core region, and global input/output lines are disposed from the interface region to the core region.
The configurations of the cell arrays and the data paths vary according to a size and a performance of a semiconductor memory device.
In a conventional cell array structure, data stored in a plurality of cells shares a single segment input/output line through respective bit line sense amplifiers (BLSA). For a shared bit line sense amplifier structure where the bit line sense amplifier array is shared between upper cell arrays and lower cell arrays, there are bit line connectors for selectively connecting the bit line sense amplifiers and the upper/lower bit lines. Accordingly, data in the two upper and lower cell array blocks sharing the bit line sense amplifier may also share the segment input/output line.
The segment input/output lines are connected to local input/output lines through input/output switches. This is aimed to prevent the segment input/output lines from being affected by a very high capacitance of the local input/output lines. Therefore, all the segment input/output lines are connected to local input/output lines through input/output switches.
The input/output switches are disposed in sub hole regions in the semiconductor memory device. The sub hole region refers to a region where a bit line sense amplifier array horizontally arranged between upper/lower cell arrays and a sub word line driver array vertically arranged between left/right cell arrays cross each other. A bit line sense amplifier drive circuit, a bit line control circuit and a sub word line control circuit, as well as the above described input/output switch, are disposed in the sub hole region.
FIGS. 1A, 1B, and 1C show a typical bank architecture of a semiconductor memory device. FIGS. 1A, 1B, and 1C are parts of a single diagram. That is, the top of FIG. 1B is coupled to the bottom of FIG. 1A and the bottom of FIG. 1B is coupled to the top of FIG. 5C, to form the single diagram.
Referring to FIGS. 1A, 1B, and 1C, a plurality of cell arrays (MAT) and sub word line driver arrays are disposed in a matrix form. Here, the bit line sense amplifier array is not shown for convenience.
Segment input/output lines SIO<0>/SIOB<0> and SIO<2>/SIOB<2> and segment input/output lines SIO<1>/SIOB<1> and SIO<3>/SIOB<3> are arrayed in a row direction on and under the cell array MAT, respectively. Local input/output lines LIOU<0>/LIOBU<0>, LIOU<1>/LIOBU<1>, LIOD<0>/LIOBD<0> and LIOD<1>/LIOBD<1>, and local input/output lines LIOU<2>/LIOBU<2>, LIOU<3>/LIOBU<3>, LIOD<2>/LIOBD<2> and LIOD<3>/LIOBD<3> are arrayed in a column direction between the cell arrays MAT, respectively.
Even if only the match up of the segment input/output lines SIO<0>/SIOB<0>, SIO<2>/SIOB<2>, SIO<1>/SIOB<1> and SIO<3>/SIOB<3> and the local input/output lines LIOU<0>/LIOBU<0>, LIOU<1>/LIOBU<1>, LIOD<0>/LIOBD<0> and LIOD<1>/LIOBD<1> are considered, the shapes of the input/output switches (disposed in the sub hole regions) connecting the segment input/output lines and the local input/output lines are different according to the bank zones.
In more detail, a middle bank zone includes a first input/output switch 51A for connecting the segment input output lines SIO and SIOB and the upper local input/output lines LIOU and LIOBU, and a second input/output switch 51B for connecting the segment input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD.
An upper bank zone includes only the first input/output switch 51A for connecting the segment input output lines SIO and SIOB and the upper local input/output lines LIOU and LIOBU.
A lower bank zone includes only a second input/output switch 51B for connecting the segment input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD.
For reference, precharging units LIO PRECHARGE are disposed at upper ends of the local input/output lines, respectively, in the upper bank zone.
FIGS. 2A, 2B, and 2C are circuit diagrams showing conventional sub hole regions of respective bank zones.
Each sub hole region includes a bit line separation signal (BISH and BISL) generation circuit 10, a sub word line drive signal (FX0, FX2, FX4 and FX6) generation circuit 11, a bit line equalizing signal (BLEQ) generation circuit 12, a bit line sense amplifier drive circuit 13, and one of input/output switch circuits 14A, 14B and 14C. Here, the circuits for the bit line separation signal (BISH and BISL) generation circuit 10, the sub word line drive signal (FX0, FX2, FX4 and FX6) generation circuit 11, the bit line equalizing signal (BLEQ) generation circuit 12, and the bit line sense amplifier drive circuit 13 are the same, respectively, regardless of the bank zones in which they are located.
Referring to FIG. 2A, the input/output switch circuit 14A disposed in the sub hole region in the upper bank zone includes transistors (three NMOS transistors each receiving the bit line equalizing signal BLEQ at their gates) for equalizing/precharging the segment input/output lines SIO and SIOB, and a first input/output switch 51A for connecting the segment input/output lines SIO and SIOB and the upper local input/output lines LIOU and LIOBU in response to an upper switch control signal IOSWU. This is because the connection between the lower local input/output lines LIOD and LIOBD and the segment input/output lines SIO and SIOB is not required in the upper bank zone. The first input/output switch 51A includes two NMOS transistors with gates for receiving the upper switch control signal IOSWU and sources/drains connected to the segment input/output lines SIO and SIOB and the upper local input/output lines LIOU and LIOBU.
Referring to FIG. 2B, the input/output switch circuit 14B disposed in the sub hole region in the middle bank zone includes transistors for equalizing/precharging the segment input/output lines SIO and SIOB, the first input/output switch 51A and a second input/output switch 51B. This is because the connection from the segment input/output lines SIO and SIOB to the upper local input/output lines LIOU and LIOBU and the lower local input/output lines LIOD and LIOBD is required in the middle bank zone. The second input/output switch 51B includes two NMOS transistors with gates for receiving the lower switch control signal IOSWD and sources/drains connected to the segment input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD.
Referring to FIG. 2C, the input/output switch circuit 14C disposed in the sub hole region in the lower bank zone includes transistors for equalizing/precharging the segment input/output lines SIO and SIOB, and the second input/output switch 51B for connecting the segment input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD in response to the lower switch control signal IOSWD. This is because the connection between the upper local input/output lines LIOU and LIOBU and the segment input/output lines SIO and SIOB is not required in the lower bank zone.
As described above, the circuits for the input/output switch circuits 14A, 14B, and 14C disposed in the sub hole regions are different according to the bank zones.
FIGS. 3A, 3B, and 3C are diagrams showing pattern layouts of sub hole regions of FIGS. 2A, 2B, and 2C, respectively. Here, a plurality of rectangles highlighted by light colors represent transistors.
As can be seen in FIGS. 3A, 3B, and 3C, the layouts of the sub hole regions are different according to the upper bank zone, the middle bank zone and the lower bank zone.
That is, the sub hole region in the upper bank zone includes only the first input/output switch 51A and does not include the second input/output switch 51B. Accordingly, the area A for the second input/output switch 51B is occupied with a vacant space or another pattern.
On the contrary, the sub hole region in the lower bank zone includes only the second input/output switch 51B and does not include the first input/output switch 51A. Accordingly, the area B for the first input/output switch 51A is occupied with a vacant space or another pattern.
Resultantly, a single bank needs a variety of layouts for sub hole regions including the input/output switch circuits 14A, 14B, and 14C.
In this case, the variety of the layout patterns may decrease the layout efficiency and increase an operation time during manufacturing. Furthermore, the variety of the layout patterns may cause operation errors in a mask process. As a result, productivity and device reliability may be decreased.